1. Field of the Disclosure
The present disclosure generally relates to processing systems and, more particularly, to cache coherency in processing systems.
2. Description of the Related Art
Processing systems generally implement system memory as a device separate from the devices implementing processors, input/output (I/O) components, and other components. Such systems therefore are often bandwidth-limited due to the volume of traffic on the interconnect connecting the system memory to the other components and latency-limited due to the propagation delay of the signaling traversing the relatively-long interconnect and the handshaking process needed to conduct such signaling. The inter-device bandwidth and inter-device latency have a particular impact on processing efficiency and power consumption of the system when a performed task requires multiple accesses to system memory, as each access requires a back-and-forth communication between the system memory and the requesting device and thus the inter-device bandwidth and latency penalties are incurred twice for each access. This problem is exacerbated in processing systems implementing cache coherency protocols for shared memory, as the processor-initiated coherency operations implemented in conventional cache coherency protocols typically make relatively heavy use of the memory interconnect and thus are significant sources of decreased memory interconnect bandwidth and increased memory interconnect latency.